module sigma_16p (
        data_in,
        syn_in,
        clk,
        res,
        data_out,
        syn_out
);
input[7:0]      data_in;//采样信号
input           syn_in;//采样时钟
input           clk;
input           res;
output[11:0]    data_out;//输出
output          syn_out;//输出同步脉冲
reg [11:0] data_out;
reg syn_out;
reg[3:0] con_syn;//采样脉冲计数
reg [11:0] sigma;//累加

wire [7:0] comp_8;//补码
wire [11:0] d_12;//升位
reg syn_in_n1;//反转延时
wire syn_pulse;//采样脉冲
assign syn_pulse=syn_in&syn_in_n1;
always @(posedge clk or negedge res) begin
    if (res==0) begin
        syn_in_n1<=0;
        con_syn<=0;
        sigma<=0;
        data_out<=0;
        syn_out<=0;
    end else begin
        syn_in_n1<=~syn_in;
        if (syn_pulse==1) begin
            con_syn<=con_syn+1;
            if (con_syn==15) begin
                sigma<=d_12;
                data_out<=sigma;
                syn_out<=1; 
            end else begin
                if (syn_pulse==1) begin
                    sigma<=sigma+d_12;
                end            
        end
        end else begin
            syn_out<=0;
        end

        
    end
end

assign comp_8=data_in[7]?{data_in[7],~data_in[6:0]+1}:data_in;
assign d_12={{4{comp_8[7]}},comp_8};


endmodule

//tb
`timescale 1ns/10ps
module sigma_16p_tb ();
reg clk;
reg res;
reg syn_in;
reg[11:0] data_in;
wire[11:0] data_out;
wire syn_out;
    sigma_16p s16p(
        .data_in(data_in),
        .syn_in(syn_in),
        .clk(clk),
        .res(res),
        .data_out(data_out),
        .syn_out(syn_out)
);

initial begin
            clk<=0;res<=0;data_in<=1;syn_in<=1;
    #17     res<=1;
    #10000   $stop;
end

always #5 clk=~clk;

always #100 syn_in=~syn_in;


endmodule
